R1621 Datasheet, PDF (2/4 Pages) RDC Semiconductor – FAST ETHERNET RISC PROCESSOR

RDC®
RISC DSP Communication
R1621
FAST ETHERNET RISC PROCESSOR
1. Features
l CPU Core
- RDC's proprietary RISC architecture
- Five-stage pipeline
- Operation frequency: 100MHz
- Supports an 8K-byte uniform cache
- Supports CPU ID
- Supports 40 PIO pins
l Two independent DMA channels
l Fast Ethernet MAC Ports
- 2-port Fast Ethernet MAC with MII interface
- The MAC packet buffer is cacheable with
snooping function
l Bus Interface
- Supports non-multiplexed address bus A[19:0]
- With 8-bit or 16-bit boot ROM bus size
- Supports an independent data/address bus for
external I/O devices
- 8-bit or 16-bit external bus dynamic access
l PCMCIA Bus Interface
- Supports a glueless and simplified 16-bit
PCMCIA bus interface
l ROM/RAM/SDRAM Controller and Addressing
Space
- Supports 16-bit data bus [15:0]
- 1M-byte memory address space Address[19:0]
- SDRAM control interface
- 64K-byte I/O space
l Interrupt Controller
- The interrupt controller with five maskable
external interrupts
l Programmable Chip-select Logic
- Programmable chip-select logic for memory or
I/O bus cycle decoder
l Programmable Wait-state Generators
l Counter/Timers
- Three independent 16-bit timers and one
independent programmable watchdog timer
l Operating Voltage Range
- Core voltage: 2.5V ± 5%
- I/O voltage: 3.3V ± 10%
l Compatible UART Channels
- Supports two compatible UART serial channels
with 16-byte FIFOs and hardware flow-control
l Package Type
128-pin PQFP
Specifications subject to change without notice, contact your sales representatives for the most update information.
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REV 1.0 Aug. 18 2005