R1620 Datasheet, PDF (2/5 Pages) RDC Semiconductor – FAST ETHERNET RISC PROCESSOR

RDC®
RISC DSP Communication
R1620
FAST ETHERNET RISC PROCESSOR
1. Features
l Five-stage pipeline
l RISC architecture
l Bus interface
- Multiplexed address and Data bus
- Supports non-multiplexed address bus A[19:0]
- 8-bit or 16-bit external bus dynamic access
- 1M-byte memory address space
- 64K-byte I/O space
- Supports an independent bus for slower I/O
device
l Software is compatible with the 80C186
microprocessor
l Supports two 16550 UART serial channel with 16
bytes FIFO.
l Supports CPU ID
l Supports 32 PIO pins
l SDRAM control Interface
l Three independent 16-bit timers and one independent
programmable watchdog timer
l The Interrupt controller with six maskable external
interrupts and two non-maskable external
interrupt
l Two independent DMA channels
l Programmable chip-select logic for Memory or
I/O bus cycle decoder
l Programmable wait-state generator
l With 8-bit or 16-bit Boot ROM bus size
l 2-Port Fast Ethernet MAC with MII interface
l With 25MHz input frequency and up to 4x25MHz
maximum internal frequency.
l Compatible with 3.3V I/O.
l Package Types include 160-pin PQFP and 160-pin
LQFP.
Specifications subject to change without notice, contact your sales representatives for the most update information.
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REV 1.0 Sep. 20 2006