R1610 Datasheet, PDF (2/4 Pages) RDC Semiconductor – FAST ETHERNET RISC PROCESSOR

RDC®
RISC DSP Communication
R1610
FAST ETHERNET RISC PROCESSOR
1. Features
l Five-stage pipeline
l RISC architecture
l Bus interface
- Multiplexed address and data bus
- Supports non-multiplexed address bus A[19:0]
- 8-bit or 16-bit external bus dynamic access
- 1M-byte memory address space
- 64K-byte I/O space
- Supports an independent bus for the slower I/O
device
l Software is compatible with the 80C186
microprocessor
l Supports two 16550 UART serial channels with
16-byte FIFO
l Supports CPU ID
l Supports 18 PIO pins
l SDRAM control Interface
l Three independent 16-bit timers and one independent
programmable watchdog timer
l The Interrupt controller with five maskable
external interrupts and one non-maskable external
interrupt
l Two independent DMA channels
l Programmable chip-select logic for memory or I/O
bus cycle decoder
l Programmable wait-state generators
l With 8-bit or 16-bit boot ROM bus size
l 1-port Fast Ethernet MAC with MII interface
l With 25MHz input frequency and up to 4x25MHz
maximum internal frequency
l Compatible with 3.3V I/O
l With 128-pin PQFP package type
Specifications subject to change without notice, contact your sales representatives for the most update information.
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REV 1.0 Nov. 25 2005