VRS51L2070 Datasheet, PDF (57/99 Pages) Ramtron International Corporation – High-Performance Versa 8051 MCU

VRS51L2070
When in master mode, the I²C interface can be forced
to generate a start condition after the next data
acknowledge phase. This is done by setting the
I2CMASTART bit to 1.
When the MASTRARB bit is set to 1, communications
of the I²C will be monitored and an interrupt will be
generated if arbitration with slave devices on the bus is
lost. The interrupt flag associated with this process is
the I2CERROR bit of the I2CSTATUS register.
If the I2CRXSTOP bit is set to 1, the I²C interface will
not acknowledge after reception of the next byte, but
will generate a stop condition instead. This will, in
effect, end the transaction with the master device.
When the I²C interface is configured as a master and
the I2CSCLLOW bit of the I2CCONFIG register is set
to 1, the SCL line will be driven low during the next
data acknowledge phase. This feature enables the
user to add the equivalent of wait states to the transfer
in order to support “slow” devices connected to the I²C
bus.
The I²C interface includes support for four interrupt
conditions via two interrupt vectors.
• RX Data Available
• RX Overrun
• TX Empty
• Master lost arbitration
The following table summarizes the possible interrupt
sources at the I²C interface level.
TABLE 103: I²C INTERRUPT SOURCES
I²C Interrupt
I2CCONFIG bit
(Set to 1 to activate)
RX Data
Available
RX Overrun
I2CRXAVEN
I2CRXOVEN
TX Empty
I2CTXEEN
Master Lost
Arbitration
MASTRARB
Interrupt
Vector
4Bh
(Int 9)
0x4B
(Int 9)
0x4B
(Int 9)
0x53
(Int 10)
To activate the I²C interface interrupts, the
corresponding enable bit of the I2CCONFIG register
must be set to 1. This will allow the I²C interrupt to
propagate to the VRS51L2070’s interrupt controller. In
order for the I²C interrupt to be recognized by the
processor, the corresponding bit of the INTEN2 and
INTSRC2 registers must be configured accordingly.
See the VRS51L2070 interrupt section for more
details.
10.4 I²C Timing Control Register
The I2CTIMING register controls the communication
speed when the I²C interface is configured in master
mode. When in slave mode, it defines the values of the
setup and hold times.
TABLE 104:I²C TIMING REGISTER - I2CTIMING SFR D2H
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
1
0
0
Bit Mnemonic Description
7:0
I2CTIMING[7:0] I²C master/slave timing configuration register
See Below
The following formulas demonstrate the impact of the
I2CTIMING value on the communication speed and
setup/hold times.
In master mode:
SCL period =
I2CCLK
32*( I2CTIMING[7:0] + 1)
The following table provides examples of the
I2CTIMING values and the corresponding
communication speed:
TABLE 105: I²C COMMUNICATION SPEED VS. I2CTIMING REGISTER VALUE (FOSC = 40MHZ)
I2CTIMING
00h
02h
0Ch (Reset)
7Ch
FFh
I2C Com Speed
1.25 MHz
416.77 kHz
96.15 kHz
10kHz
4.88kHz
In slave mode:
Set-up/Hold Time = I2CCLKperiod * I2CTIMING[7:0]
In this case, the precision is: 2 x I2CCLKperiod
TABLE 106: I²C SETUP AND HOLD TIME VS. I2CTIMING REGISTER VALUE (FOSC = 40MHZ)
I2CTIMING
00h
0Ch
FFh
Setup/Hold
Time
0 uS
0.3 uS
6.38 uS
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