AN92584 Datasheet, PDF (3/42 Pages) Ramtron International Corporation – Designing for Low Power and Estimating Battery Life for BLE Applications

Designing for Low Power and Estimating Battery Life for BLE Applications
Clock
Source
IMO
ECO
WCO
ILO
Frequency
Table 1. System Clocks
System Requirements
System Constraints
APIs
3 MHz -48 MHz Used to run the CPU and all other
peripherals
Either the IMO or ECO is required ^{ON – CySysClkImoStart()}
to run the CPU.
The CPU must use the IMO while
performing flash write operations. ^{OFF – CySysClkImoStop()}
24 MHz
Used by BLE subsystem (BLESS) for
packet transmissions and reception.
Can also be used to run the CPU
Either the IMO or ECO is required ^{ON – CySysClkEcoStart()}
to run the CPU.
OFF – CySysClkEcoStop()
32 kHz
Used by BLESS to maintain link
timing. Can also be used to run the
watchdog timer
Either the WCO or ILO is required ^{ON – CySysClkWcoStart()}
to run the watchdog timer.
OFF – CySysClkWcoStop()
32 kHz
Can be used to run the watchdog
timer if WCO is not available
The ILO cannot be used for
BLESS link timing.
ON – CySysClkIloStart()
OFF – CySysClkIloStop()
2.2 System Power Modes
PSoC 4/PRoC BLE devices support five system power modes. Table 2 summarizes these modes, their currents,
active components, wakeup sources, and the APIs available to put the system into one of the low-power modes.
Table 2. System Power Modes
System Current
Code RAM
Digital
Analog Clock Wakeup Wakeup Wakeup
API
Power Consumption Execution Available Peripherals Peripherals Sources Sources Time State
Mode
Available Available Available
Active 850 µA +
Yes
ON
All
All
All
–
260 µA per
MHz
–
–
–
Sleep 850 µA +
No
60 µA per
MHz
Deep- 1.3 µA
No
Sleep
Retention All
All
All
Any
0
Active CySysPmSleep()
interrupt
source
Retention WDT¹,
LP
WCO⁶,
LCD²,
Comparator, ILO⁷
SCB(I²C/SPI CTBm¹¹,
only),
POR⁴,
BLESS³
BOD⁵
LP
25 µs
Comparator,
GPIO⁸,
CTBm,
BLESS³,
WDT, SCB⁹
Active
CySysPmDeepSleep()
Hibernate 150 nA
No
Retention No
LP
None
Comparator,
POR, BOD
LP
2 ms
Comparator,
GPIO
Chip CySysPmHibernate()
Reset
Stop
60 nA
No
OFF
No
No
None WAKEUP, 2 ms Chip CySysPmStop()
XRES¹⁰ pins
Reset
1 _{Watchdog timer}
2 _{Liquid crystal display}
3 _{BLE subsystem}
10 _{External reset}
4 _{Power-on reset}
5 _{Brownout detect}
6 _{32-kHz watch crystal oscillator}
11 _{Continuous time block mini}
7 _{32-kHz internal low-speed oscillator}
8 _{General-purpose input/output}
9 _{Serial communication block}
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Document No. 001-92584 Rev. *A
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