English
Language : 

U6264A Datasheet, PDF (5/9 Pages) –
◁
Switching Characteristics
Time to Output in Low-Z
Cycle Time
Write Cycle Time
Read Cycle Time
Access Time
E1 LOW or E2 HIGH to Data Valid
G LO W to Data Valid
Address to Data Valid
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
Data Hold Time
Address Hold from End of Write
Output Hold Time from Address
Change
E1 HIGH or E2 LOW to Output in
High-Z
W LOW to Output in High-Z
G HIGH to Output in High-Z
Symbol
Alt.
IEC
tLZ
tt(QX)
tWC
tcW
tRC
tcR
tACE
tOE
tAA
ta(E)
ta(G)
ta(A)
tWP
tw(W)
tCW
tw(E)
tAS
tsu(A)
tCW
tsu(E)
tWP
tsu(W)
tDS
tsu(D)
tDH
th(D)
tAH
th(A)
tOH
tv(A)
tHZCE
tHZWE
tHZOE
tdis(E)
tdis(W)
tdis(G)
Min.
07
10
5
5
70
100
70
100
-
-
-
-
-
-
50
70
65
90
0
0
65
90
50
70
35
40
0
0
0
0
5
5
0
0
0
0
0
0
U6264A
Max.
07
10
10
10
Unit
ns
ns
ns
70
100
ns
40
50
ns
70
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
35
ns
30
35
ns
25
35
ns
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
4.5 V
VCC
4.5 V
VCC
VCC(DR) ≥ 2 V
2.2 V
tDR
Data Retention
trec
0V
VCC(DR) ≥ 2 V
E2
2.2 V
tDR
Data Retention
trec
E1
0.8 V
VE2(DR) ≤ 0.2 V
0.8 V
0
VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
December 12, 1997
tDR:
min 0 ns
trec:
min tcR
5
 ▷