HYS72T1G242EP Datasheet, PDF (5/43 Pages) Qimonda AG – 240-Pin Dual Die Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
2
Pin Configuration and Block Diagrams
This chapter contains the pin configuration and block diagrams.
2.1
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1.
Pin No.
Clock Signals
185
186
Name
CK0
CK0
52
CKE0
171
CKE1
NC
Control Signals
193
S0
76
S1
NC
Pin Buffer Function
Type Type
TABLE 5
Pin Configuration of RDIMM
I
SSTL Clock Signal CK0, Complementary Clock Signal CK0
I
SSTL ^{The system clock inputs. All address and command lines are sampled}
on the cross point of the rising edge of CK and the falling edge of CK.
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to the input clock.
I
SSTL Clock Enables 1:0
I
SSTL ^{Activates the DDR2 SDRAM CK signal when HIGH and deactivates}
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
Note: 2-Ranks module
NC —
Not Connected
Note: 1-Rank module
I
SSTL Chip Select
I
SSTL ^{Enables the associated DDR2 SDRAM command decoder when LOW}
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue.
Rank 0 is selected by S0
Rank 1 is selected by S1
The input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When S is HIGH,
all register outputs (except CK, ODT and Chip select) remain in the
previous state.
Note: 2-Ranks module
NC —
Not Connected
Note: 1-Rank module
Rev. 1.0, 2007-07
5
07242007-LR08-OZC0