HYS72T1G242EP Datasheet, PDF (36/43 Pages) Qimonda AG – 240-Pin Dual Die Registered DDR2 SDRAM Modules

Product Type
Internet Data Sheet
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Organization
Label Code
JEDEC SPD Revision
Byte#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Description
t_WTR.MIN [ns]
t_RTP.MIN [ns]
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
8 GByte 8 GByte 8 GByte 8 GByte 8 GByte
×72
×72
×72
×72
×72
4 Ranks 4 Ranks 4 Ranks 4 Ranks 4 Ranks
(×4)
(×4)
(×4)
(×4)
(×4)
PC2–
6400P–
666
PC2–
6400P–
555
PC2–
5300P–
444
PC2–
5300P–
555
PC2–
4200P–
444
Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2 Rev. 1.2
HEX
1E
1E
00
06
3C
7F
80
14
1E
0F
51
60
4F
39
3D
2C
35
24
46
24
27
C4
8C
70
HEX
1E
1E
00
36
39
7F
80
14
1E
0F
51
60
4F
39
3D
2C
35
24
46
24
27
C4
8C
70
HEX
1E
1E
00
06
39
7F
80
18
22
0F
51
60
47
34
3D
28
31
24
3E
22
24
C4
8C
68
HEX
1E
1E
00
06
3C
7F
80
18
22
0F
51
60
47
34
3D
28
31
24
3E
22
23
C4
8C
68
HEX
1E
1E
00
06
3C
7F
80
1E
28
0F
51
60
3F
31
3D
23
2C
24
36
22
24
C4
8C
61
Rev. 1.0, 2007-07
36
07242007-LR08-OZC0