HYS64T32000EU-25F-B2 Datasheet, PDF (5/95 Pages) Qimonda AG – 240-Pin unbuffered DDR2 SDRAM Modules

Internet Data Sheet
HYS[64/72]T[32/64/128][0/9]xxEU-[25F/2.5/3/3S/3.7]-B2
Unbuffered DDR2 SDRAM Module
Product Type¹⁾
Compliance Code²⁾
Description
SDRAM
Technology
HYS64T128020EU–3–B2
HYS64T128920EU–3–B2
1GB 2R×8 PC2–5300U–444–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020EU–3–B2
HYS72T128920EU–3–B2
1GB 2R× 8 PC2-5300E–444–12–G0
2 Ranks, ECC
512 Mbit (×8)
PC2–5300
HYS64T32000EU–3S–B2
HYS64T32900EU–3S–B2
256MB 1R×16 PC2–5300U–555–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000EU–3S–B2
HYS64T64900EU–3S–B2
512MB 1R×8 PC2–5300U–555–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000EU–3S–B2
HYS72T64900EU–3S–B2
512MB 1R×8 PC2–5300E–555–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020EU–3S–B2
HYS64T128920EU–3S–B2
1GB 2R×8 PC2–5300U–555–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020EU–3S–B2
HYS72T128920EU–3S–B2
1GB 2R×8 PC2–5300E–555–12–G0
2 Ranks, ECC
512 Mbit (×8)
PC2–4200
HYS64T32000EU–3.7–B2
HYS64T32900EU–3.7–B2
256MB 1R×16 PC2–4200U–444–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000EU–3.7–B2
HYS64T64900EU–3.7–B2
512MB 1R×8 PC2–4200U–444–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000EU–3.7–B2
HYS72T64900EU–3.7–B2
512MB 1R×8 PC2–4200E–444–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020EU–3.7–B2
HYS64T128920EU–3.7–B2
1GB 2R×8 PC2–4200U–444–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020EU–3.7–B2
HYS72T128920EU–3.7–B2
1GB 2R×8 PC2–4200E–444–12–G0
2 Ranks, ECC
512 Mbit (×8)
1) All Product Type end with a place code, designating the silicon die revision. Example: HYS64T64000EU–3–B2, indicating Rev. “B2” dies
are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200U–444–12–D0”, where
4200U means Unbuffered DIMM modules with 4.26 GB/sec. Module Bandwidth and “444-12-D0” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “D”.
Rev. 1.0, 2006-10
5
10202006-L0SM-FEYT