HYS72T256023 Datasheet, PDF (4/41 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
1.2
Description
The QIMONDA HYS72T[512/256]02xHR–[3S/3.7/5]–A
module family are Registered DIMM modules “RDIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as ECC modules in 256M × 72 (2 GByte),
512M × 72 (4 GByte) organization and density, intended for
mounting into 240-Pin connector sockets.
The memory array is designed with stacked 1-Gbit Double-
Data-Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E²PROM device using the 2-pin I²C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
Product Type¹⁾
Compliance Code²⁾
TABLE 2
Ordering Information for RoHS Compliant Products
Description SDRAM Technology
PC2–5300
HYS72T512022HR–3S–A
4 GB 2R×4 PC2–5300R–555–12–D0
2 Ranks, ECC 1 Gbit (×4)
PC2–4200
HYS72T512022HR–3.7–A
4 GB 2R×4 PC2–4200R–444–12–D0
2 Ranks, ECC 1 Gbit (×4)
PC2-3200
HYS72T256023HR–5–A
2 GB 2R×8 PC2–3200R–333–12–ZZ
2 Ranks, ECC 1 Gbit (×8)
HYS72T512022HR–5–A
4 GB 2R×4 PC2–3200R–333–12–D0
2 Ranks, ECC 1 Gbit (×4)
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS72T512022HR–3.7–A, indicating Rev.
“A” dies are used for DDR2 SDRAM components. For all QIMONDA DDR2 module and component nomenclature see Chapter 6 of this
data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–D0”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced
on the Raw Card “D”
DIMM
Density
2 GB
4 GB
Module
Organization
256M × 72
512M × 72
Memory
Ranks
2
2
ECC/
Non-ECC
ECC
ECC
# of
SDRAMs
2×9
2 × 18
TABLE 3
Address Format
# of row/bank/columns bits Raw Card
14/3/10
Z
14/3/11
D
Product Type
DRAM Components
DRAM Density
TABLE 4
Components on Modules
DRAM Organization Note¹⁾
HYS72T256023HR
HYB18T2G802AF
2 Gbit
2 × 128M × 8
HYS72T512022HR
HYB18T2G402AF
2 Gbit
2 × 256M × 4
1) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.
Rev. 1.2, 2007-01
4
03292006-AYVF-ZIIJ