HYS64T256022EDL Datasheet, PDF (4/40 Pages) Qimonda AG – 200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules

Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
module family are Small Outline modules “SO-DIMMs” with
30 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 256M × 64 (2 GB)
organization and density, intended for mounting into 200-pin
connector sockets.
The memory array is designed with stacked 1 Gbit Double-
Data-Rate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB. The DIMMs feature
serial presence detect based on a serial E²PROM device
using the 2-pin I²C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
Product Type¹⁾
Compliance Code²⁾
TABLE 2
Ordering Information for RoHS Compliant Products
Description
SDRAM Technology
PC2–6400
HYS64T256022EDL–25F–B 2GB 2R×8 PC2–6400S–555–12–D0
2 Ranks, Non-ECC 1 Gbit (×8)
PC2–6400
HYS64T256022EDL–2.5–B 2GB 2R×8 PC2–6400S–666–12–D0
2 Ranks, Non-ECC 1 Gbit (×8)
PC2–5300
HYS64T256022EDL–3–B
2GB 2R×8 PC2–5300S–444–12–D0
2 Ranks, Non-ECC 1 Gbit (×8)
PC2–5300
HYS64T256022EDL–3S–B 2GB 2R×8 PC2–5300S–555–12–D0
2 Ranks, Non-ECC 1 Gbit (×8)
PC2–4200
HYS64T256022EDL–3.7–B 2GB 2R×8 PC2–4200S–444–12–D0
2 Ranks, Non-ECC 1 Gbit (×8)
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T256022EDL–3.7–B, indicating
Rev. “B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of
this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200S–444–12–D0”, where
4200S means SO-DIMM modules with 4.26 GB/sec Module Bandwidth and “444–12” means Column Address Strobe (CAS) latency = 4,
Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on
the Raw Card “D”.
DIMM Density Module
Organization
2 GByte
256M ×64
Memory ECC/
Ranks Non-ECC
2
Non-ECC
# of
SDRAMs
16
TABLE 3
Address Format
# of row/bank/columns bits Raw Card
14/3/10
D
TABLE 4
Components on Modules
Product Type¹⁾
DRAM Components¹⁾
DRAM Density
DRAM Organisation
Note
HYS64T256022EDL
HYB18T2G802BF
2 ×1 Gbit
2× 128M ×8
2)
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2006-11
4
11172006-DXYK-2PPW