HYS64T256022EDL Datasheet, PDF (23/40 Pages) Qimonda AG – 200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules

Internet Data Sheet
HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B
Small Outline DDR2 SDRAM Modules
W+=
W536 7 H QG SRLQW
92+ [P9 
92+ [P9 
92/ [P9 
92/ [P9 
7 7
W+=W536 7 HQG SRLQ W  77 
FIGURE 2
Method for calculating transitions and endpoint
977[P9
977[P9
977[P 9
977[P9
W/=
W53 5(EHJLQSRLQW
7 7
W/=W535( E HJLQ SRLQ W  7 7 
FIGURE 3
Differential input waveform timing - t_DS and t_DS
'46
'46 
W'6 W'+
W'6  W'+
9_' _{'4 }
9_,_+DF _PLQ 
9_,_+GF _PLQ 
9₅ _()GF
9_,_/GF _PD[ 
9_,_/DF _PD[ 
9₆ _6
FIGURE 4
Differential input waveform timing - t_lS and t_lH
&.
&.
W,6  W,+ 
W,6 W,+ 
9_' _{'4 }
9_,_{+DF }PLQ
9_,_{+GF }PLQ
9₅ _()GF
9_,_{/GF }PD[ 
9_,_{/DF }PD[ 
9₆ _6
Rev. 1.0, 2006-11
23
11172006-DXYK-2PPW