HYS64D64020HBDL-5-C Datasheet, PDF (4/30 Pages) Qimonda AG – 200-Pin Small Outline Dual-In-Line Memory Modules

Internet Data Sheet
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
1.2
Description
The HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–
C are industry standard 200-Pin Small Outline Dual-In-Line
Memory Modules (SO-DIMMs) organized as 64M ×64. The
memory array is designed with Double Data Rate
Synchronous DRAMs (DDR SDRAM). A variety of decoupling
capacitors are mounted on the PC board. The DIMMs feature
serial presence detect based on a serial E²PROM device
using the 2-pin I²C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
Type
PC3200 (CL=3.0)
HYS64D64020GBDL–5–C
PC2700 (CL=2.5)
HYS64D64020GBDL–6–C
Compliance Code
PC3200S–3033–1–Z
PC2700S–2533–0–Z
Description
TABLE 2
Ordering Information
SDRAM
Technology
Two ranks 512 MB SO-DIMM
Two ranks 512 MB SO-DIMM
32 MBit (×8)
32 MBit (×8)
Product Type ¹⁾
Compliance Code
TABLE 3
Ordering Information for RoHS Compliant Products
Description
SDRAM Technology
PC3200 (CL=3.0)
HYS64D64020HBDL–5–C
PC3200S–3033–1–Z
Two ranks 512 MB SO-DIMM
32 MBit (×8)
PC2700 (CL=2.5)
HYS64D64020HBDL–6–C
PC2700S–2533–0–Z
Two ranks 512 MB SO-DIMM
32 MBit (×8)
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on request.
Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2. The Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the latencies and
SPD code definition (for example “2033–0” means CAS latency of 2.0 clocks, RCD ¹⁾ latency of 3 clocks, Row Precharge
latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Rev. 1.21, 2007-01
4
03292006-F1IB-1I3E