HYS64D64020HBDL-5-C Datasheet, PDF (3/30 Pages) Qimonda AG – 200-Pin Small Outline Dual-In-Line Memory Modules

Internet Data Sheet
1
Overview
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
This chapter lists all main features of the product family HYS64D64020[H/G]BDL–[5/6]–C and the ordering information.
1.1
Features
• Non-parity 200-Pin Small Outline Dual-In-Line Memory
Modules
• Two ranks 64M × 64 Organization
• JEDEC standard Double Data Rate Synchronous DRAMs
(DDR SDRAM)
• Single +2.5 V (± 0.2 V) Power Supply and Single +2.6 V
(± 0.1 V) Power Supply for DDR400
• Built with 256 Mbit DDR SDRAMs Organised as × 8 in
P–TFBGA–60 Packages
• Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• RAS-lockout Supported t_RAP=t_RCD
• All Inputs and Outputs SSTL_2 Compatible
• Serial Presence Detect with E²PROM
• Jedec Standard form Factor:
67.60 mm × 31.75 mm × 3.80 mm
• Gold Plated Contacts
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
Module
@CL3
@CL2.5
@CL2
f_CK3
f_CK2.5
f_CK2
–5
DDR400B
PC3200–3033
200
166
133
–6
DDR333B
PC2700–2533
166
166
133
TABLE 1
Performance
Unit
—
—
MHz
MHz
MHz
Rev. 1.21, 2007-01
3
03292006-F1IB-1I3E