HYS64T32000HU-25F-B Datasheet, PDF (35/87 Pages) Qimonda AG – 240-Pin unbuffered DDR2 SDRAM Modules

Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
3.4
I_DD Specifications and Conditions
List of tables defining I_DD Specifications and Conditions.
• Table 22 “IDD Measurement Conditions” on Page 35
• Table 23 “Definitions for IDD” on Page 36
• Table 25 “IDD Specification for HYS[64/72]T[32/64/128]0x0HU-2.5-B” on Page 38
• Table 26 “IDD Specification for HYS[64/72]T[32/64/128]0x0HU-3-B” on Page 39
• Table 27 “IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3S-B” on Page 40
• Table 27 “IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3S-B” on Page 40
• Table 28 “IDD Specification for HYS[64/72]T[32/64/128]xx0HU-3.7-B” on Page 41
• Table 29 “I DD Specification for HYS[64/72]T[32/647128]0x0HU-5-B” on Page 42
Parameter
TABLE 22
I_DD Measurement Conditions
Symbol Note
1)2)3)4)5)
Operating Current 0
I_DD0
One bank Active - Precharge; t_CK = t_CK.MIN, t_RC = t_RC.MIN, t_RAS = t_RAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
I_DD1
6)
One bank Active - Read - Precharge; I_OUT = 0 mA, BL = 4, t_CK = t_CK.MIN, t_RC = t_RC.MIN, t_RAS = t_RAS.MIN,
t_RCD = t_RCD.MIN, AL = 0, CL = CL_MIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
I_DD2N
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
I_DD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; t_CK = t_CK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
I_DD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CK.MIN;
t_RAS = t_RAS.MAX, t_RP = t_RP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; I_OUT = 0 mA.
Active Power-Down Current
All banks open; t_CK = t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
I_DD3N
I_DD3P(0)
Active Power-Down Current
I_DD3P(1)
All banks open; t_CK = t_CK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
I_DD4R
6)
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CKMIN; t_RAS = t_RASMAX;
t_RP = t_RPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; I_OUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL_MIN; t_CK = t_CK.MIN;
t_RAS = t_RAS.MAX., t_RP = t_RP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
I_DD4W
Rev. 1.3, 2006-12
35
03292006-6GMD-RSFT