HYS64T32000HU-25F-B Datasheet, PDF (24/87 Pages) Qimonda AG – 240-Pin unbuffered DDR2 SDRAM Modules

Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Unbuffered DDR2 SDRAM Module
Parameter
Symbol
DDR2–667
Min.
Max.
Unit
Note
1)2)3)4)5)6)7)8)
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
t_DS.BASE
t_DSH
t_DSS
t_HP
Data-out high-impedance time from CK / CK
t_HZ
Address and control input hold time
t_IH.BASE
Control & address input pulse width for each input t_IPW
Address and control input setup time
t_IS.BASE
DQ low impedance time from CK/CK
t_LZ.DQ
DQS/DQS low-impedance time from CK / CK
t_LZ.DQS
MRS command to ODT update delay
t_MOD
Mode register set command cycle time
t_MRD
OCD drive mode output delay
t_OIT
DQ/DQS output hold time from DQS
t_QH
DQ hold skew factor
t_QHS
Read preamble
t_RPRE
Read postamble
t_RPST
Internal Read to Precharge command delay
t_RTP
Write preamble
t_WPRE
Write postamble
t_WPST
Write recovery time
t_WR
Internal write to read command delay
t_WTR
Exit power down to read command
t_XARD
Exit active power-down mode to read command t_XARDS
(slow exit, lower power)
100
0.2
0.2
Min(t_CH.ABS,
t_CL.ABS)
—
275
0.6
200
2 x t_AC.MIN
t_AC.MIN
0
2
0
t_HP – t_QHS
—
0.9
0.4
7.5
0.35
0.4
15
7.5
2
7 – AL
—
—
—
—
t_AC.MAX
—
—
—
t_AC.MAX
t_AC.MAX
12
—
12
—
340
1.1
0.6
—
—
0.6
—
—
—
—
ps
t_CK.AVG
t_CK.AVG
ps
18)19)20)
17)
17)
21)
ps
ps
t_CK.AVG
ps
ps
ps
ns
nCK
ns
ps
ps
t_CK.AVG
t_CK.AVG
ns
t_CK.AVG
t_CK.AVG
ns
ns
nCK
nCK
9)22)
25)23)
24)25)
9)22)
9)22)
31)
31)
26)
27)
28)29)
28)30)
31)
31)
31)32)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
t_XP
t_XSNR
t_XSRD
WL
2
—
t_RFC +10
—
200
—
RL–1
nCK
ns
31)
nCK
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) V_DDQ = 1.8 V ± 0.1V; V_DD = 1.8 V ± 0.1 V. See notes ^5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
7) The output timing reference voltage level is V_TT.
Rev. 1.3, 2006-12
24
03292006-6GMD-RSFT