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HYS72T64400HFN Datasheet, PDF (31/42 Pages) Qimonda AG – 240-Pin Fully-Buffered DDR2 SDRAM Modules | |||
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Product Type
Internet Data Sheet
HYS72T[64/128/256]4[00/20]HFNâ[3S/3.7]âB
Organization
512MB
1 GByte
2 GByte
Ã72
Ã72
Ã72
1 Rank (Ã8)
2 Ranks (Ã8)
2 Ranks (Ã4)
Label Code
PC2â4200Fâ444 PC2â4200Fâ444 PC2â4200Fâ444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte# Description
HEX
23
tRAS.MIN (min. Active to Precharge Time)
B4
24
tRC.MIN (min. Active to Active / Refresh Time)
F0
25
tRFC.MIN LSB (min. Refresh Recovery Time Delay)
A4
26
tRFC.MIN MSB (min. Refresh Recovery Time Delay)
01
27
tWTR.MIN (min. Internal Write to Read Cmd Delay)
1E
28
tRTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
29
Burst Lengths Supported
03
30
Terminations Supported
07
31
Drive Strength Supported
01
32
tREFI (avg. SDRAM Refresh Period)
C2
33
TCASE.MAX Delta / âT4R4W Delta
50
34
Psi(T-A) DRAM
7A
35
âT0 (DT0) DRAM
40
36
âT2Q (DT2Q) DRAM
29
37
âT2P (DT2P) DRAM
36
38
âT3N (DT3N) DRAM
21
39
âT4R (DT4R) / âT4R4W Sign (DT4R4W) DRAM
40
40
âT5B (DT5B) DRAM
1E
41
âT7 (DT7) DRAM
22
42 - 78 Not used
00
79
FBDIMM ODT Values
01
80
Not used
00
81
Channel Protocols Supported LSB
02
82
Channel Protocols Supported MSB
00
83
Back-to-Back Access Turnaround Time
10
84
AMB Read Access Delay for DDR2-800
56
HEX
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
40
29
36
21
40
1E
22
00
22
00
02
00
10
56
HEX
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
40
29
36
21
40
1E
22
00
22
00
02
00
10
58
Rev. 1.1, 2006-11
31
09142006-87TL-4SLW
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