HYS72T64000HP Datasheet, PDF (22/49 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM = RU{t_PARAM / t_CK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP = RU{t_RP / t_CK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP = 15 ns, the device will support
t_nRP = RU{t_RP / t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
36) t_WTR is at lease two clocks (2 x t_CK) independent of operation frequency.
FIGURE 2
Method for calculating transitions and endpoint
W+=
W536 7 H QG SRLQW
92+ [P9 
92+ [P9 
92/ [P9 
92/ [P9 
7 7
W+=W536 7 HQG SRLQ W  77 
977[P9
977[P9
977[P 9
977[P9
W/=
W53 5(EHJLQSRLQW
7 7
W/=W535( E HJLQ SRLQ W  7 7 
'46
'46 
&.
&.
FIGURE 3
Differential input waveform timing - t_DS and t_DS
W'6 W'+
W'6  W'+
9_' _{'4 }
9_,_+DF _PLQ 
9_,_+GF _PLQ 
6_{2 %&DC}
9_,_/GF _PD[ 
9_,_/DF _PD[ 
9₆ _6
FIGURE 4
Differential input waveform timing - t_lS and t_lH
W,6  W,+ 
W,6 W,+ 
9_' _{'4 }
9_,_{+DF }PLQ
9_,_{+GF }PLQ
9₅ _()GF
9_,_{/GF }PD[ 
9_,_{/DF }PD[ 
9₆ _6
Rev. 1.02, 2007-07
22
03292006-08VU-L8WK