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HYS72T64000HP Datasheet, PDF (17/49 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules | |||
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Internet Data Sheet
HYS72T[64/128/256]xx0HPâ[3S/3.7]âA
Registered DDR2 SDRAM Modules
3.3
Timing Characteristics
This chapter describes the AC characteristics tables.
3.3.1
Speed Grades Definitions
Speed Grade Definitions for: DDR2â667D (Table 12), DDR2â533C (Table 13)
Speed Grade
TABLE 12
Speed Grade Definition Speed Bins for DDR2â667D
DDR2â667D
Unit
Notes
QAG Sort Name
â3S
CAS-RCD-RP latencies
5â5â5
tCK
Parameter
Symbol
Min.
Max.
â
Clock Frequency
@ CL = 3
tCK
5
8
ns
1)2)3)4)
@ CL = 4
tCK
3.75
8
ns
1)2)3)4)
@ CL = 5
tCK
3
8
ns
1)2)3)4)
Row Active Time
tRAS
45
70000
ns
1)2)3)4)5)
Row Cycle Time
tRC
60
â
ns
1)2)3)4)
RAS-CAS-Delay
tRCD
15
â
ns
1)2)3)4)
Row Precharge Time
tRP
15
â
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
Rev. 1.02, 2007-07
03292006-08VU-L8WK
@ CL = 3
@ CL = 4
@ CL = 5
TABLE 13
Speed Grade Definition Speed Bins for DDR2â533C
DDR2â533C
Unit
Note
â3.7
Symbol
tCK
tCK
tCK
tRAS
tRC
4â4â4
Min.
5
3.75
3.75
45
60
Max.
8
8
8
70000
â
tCK
â
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)
ns
1)2)3)4)5)
ns
1)2)3)4)
17
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