PYA28C64B Datasheet, PDF (6/11 Pages) Pyramid Semiconductor Corporation – Access Times of 150, 200, 250 and 350ns Software Data Protection

TIMING WAVEFORM OF PAGE WRITE CYCLE
PYA28C64B - 8K x 8 EEPROM
NOTES:
• For each successive write within the page write operation, A₆-A₁₂ should be the same. Otherwise, writes to an un-
known address could occur.
• Between successive byte writes within a page write operation, OE can be strobed LOW. For example, this can be
done with CE and WE HIGH to fetch data from another memory device within the system for the next write. Alterna-
tively, this can be done with WE HIGH and CE LOW, effectively performing a polling operation.
• The timings shown above are unique to page write operations. Individual byte load operations within the page write
must conform to either the CE or WE controlled write cycle timing.
Document # EEPROM111 REV 02
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