PYA28C256 Datasheet, PDF (3/14 Pages) Pyramid Semiconductor Corporation – Access Times of 150, 200, 250 and 350ns Software Data Protection

3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable com-
mand sequence is issued. Power transitions do not dis-
able SDP and SDP will protect the PYA28C256 during
power-up and power-down conditions. All command se-
quences must conform to the page write timing specifi-
cations. The data in the enable and disable command
sequences is not written to the device and the memory
addresses used in the sequence may be written with data
in either a byte or page write operation.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
write timers. No data will be written to the device; howev-
er, for the duration of tWC, read operations will effectively
be polling operations.
DEVICE IDENTIFICATION
An extra 64 bytes of EEPROM memory are available to
the user for device identification. By raising A9 to 12V
± 0.5V and using address locations 7FC0H to 7FFFH
the additional bytes may be written to or read from in the
same manner as the regular memory array.
OPTIONAL CHIP ERASE MODE
The entire device can be erased using a 6-byte software
code. Please see "Software Chip Erase" application note
at the end of this datasheet for details.
PYA28C256 - 32K x 8 EEPROM
Document # EEPROM104 REV 03
Page 3