PYA28C256 Datasheet, PDF (11/14 Pages) Pyramid Semiconductor Corporation – Access Times of 150, 200, 250 and 350ns Software Data Protection

PYA28C256 - 32K x 8 EEPROM
APPLICATION NOTE - SOFTWARE CHIP ERASE
The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of
6-byte load commands to specific address locations with specific data patterns. Once the code has been entered, the
device will set each byte to the high state (FFH). After the software chip erase has been initiated, the device will inter-
nally time the erase operation so that no external clocks are required. The maximum time required to erase the whole
chip is t_EC (20 ms). The software data protection is still enabled even after the software chip erase is performed.
CHIP ERASE CYCLE CHARACTERISTICS
Symbol Parameter
t_EC
Chip Erase Cycle Time
20 ms Max
CHIP ERASE SOFTWARE ALGORITHM⁽¹⁾⁽³⁾
Notes:
1. Data Format: (Hex); Address Format: (Hex).
2. After loading the 6-byte code, no byte loads are allowed
until the completion of the erase cycle. The erase cycle
will time itself to completion in 20 ms (max).
3. The flow diagram shown is for a x8 part. For a x16 part,
the data should be 16 bits long (e.g., the data to be
loaded should be AAAA for step 1 in the algorithm).
CHIP ERASE CYCLE WAVEFORMS
Notes:
1. OE must be high only when WE and CE are both low.
Document # EEPROM104 REV 03
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