PYA28C010 Datasheet, PDF (2/15 Pages) Pyramid Semiconductor Corporation – Access Times of 120, 150, 200, and 250ns Single 5V±10% Power Supply

OPERATION
PYA28C010 - 128K x 8 EEPROM
READ
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning HIGH.
This two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either OE or CE is HIGH.
WRITE
Write operations are initiated when both CE and WE are LOW
and OE is HIGH. The PYA28C010 supports both a CE and WE
controlled write cycle. That is, the address is latched by the fall-
ing edge of either CE or WE, whichever occurs last. Similarly,
the data is latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation, once initi-
ated, will automatically continue to completion, typically within
5 ms.
PAGE WRITE
The page write feature of the AS28C010 allows the entire
memory to be written in 5 seconds. Page write allows two to
two hundred fifty-six bytes of data to be consecutively written
to the PYA28C010 prior to the commencement of the internal
programming cycle. The host can fetch data from another de-
vice within the system during a page write operation (change the
source address), but the page address (A₈ through A₁₆) for each
subsequent valid write cycle to the part during this operation
must be the same as the initial page address.
The page write mode can be initiated during any write opera-
tion. Following the initial byte write cycle, the host can write an
additional one to two hundred fifty-six bytes in the same manner
as the first byte was written. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin within
100µs of the falling edge of the preceding WE. If a subsequent
WE HIGH to LOW transition is not detected within 100µs, the
internal automatic programming cycle will commence. There
is no page write window limitation. Effectively the page write
window is infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
WRITE
The PYA28C010 provides the user two write operation status
bits. These can be used to optimize a system write cycle time.
The status bits are mapped onto the I/O bus as shown below.
Document # EEPROM103 REV 03
DATA POLLING
The PYA28C010 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the PYA28C010, eliminating additional
interrupts or external hardware. During the internal program-
ming cycle, any attempt to read the last byte written will produce
the complement of that data on I/O₇ (i.e., write data=0xxx xxxx,
read data=1xxx xxxx). Once the programming cycle is com-
plete, I/O₇ will reflect true data. Note: If the PYA28C010 is in
the protected state and an illegal write operation is attempted,
DATA Polling will not operate.
TOGGLE BIT
The PYA28C010 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle, I/O₆ will toggle from HIGH to LOW and LOW
to HIGH on subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the device
will be accessible for addtional read or write operations.
DATA PROTECTION
Pyramid Semiconductor has incorporated both hardware and
software features that will protect the memory against inadver-
tent writes during transitions of the host system power supply.
HARDWARE PROTECTION
Hardware features protect against inadvertent writes to the PY-
A28C010 in the following ways: (a) V_CC sense - if V_CC is below
3.8V (typical) the write function is inhibited; (b) V_CC power-on
delay - once V_CC has reached 3.8V the device will automatically
time out 5 ms (typical) before allowing a write; (c) write inhibit
- holding any one of OE low, CE high or WE high inhibits write
cycles; (d) noise filter - pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION
A software controlled data protection feature has been imple-
mented on the PYA28C010. When enabled, the software data
protection (SDP), will prevent inadvertent writes. The SDP fea-
ture may be enabled or disabled by the user; the PYA28C010 is
shipped from Pyramid Semiconductor with SDP disabled.
SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to three
specific addresses (refer to Software Data Protection Algo-
rithm). After writing the 3-byte command sequence and after
t_WC the entire PYA28C010 will be protected against inadvertent
write operations. It should be noted, that once protected the
host may still perform a byte or page write to the PYA28C010.
This is done by preceding the data to be written by the same
3-byte command sequence used to enable SDP.
Once set, SDP will remain active unless the disable command
sequence is issued. Power transitions do not disable SDP and
SDP will protect the PYA28C010 during power-up and power-
down conditions. All command sequences must conform to the
page write timing specifications. The data in the enable and
disable command sequences is not written to the device and the
memory addresses used in the sequence may be written with
data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without the
Page 2