PT9120_10 Datasheet, PDF (6/12 Pages) Princeton Technology Corp – GPS Receiver RF Front End IC

PT9120
RF LNA
Impedance matching at the PT9120’s integrated LNA’s input and output is required. At the LNA input, an optimum noise
match is required for best sensitivity performance. At the LNA output, a match to the 50Ω impedance of the SAW filter is
required. Typical matching topologies and component values are shown in Typical PT9120 RF application circuit
schematic. Note that the layout of the application PCB may affect these component values.
RF MIXER
The RF mixer down-converts the GPS signal band to a 1st IF near 20MHz (depending upon the chosen crystal reference
frequency as specified in Supported frequency plans). The RFIN input of the mixer is on-chip matched to 50Ω and is
internally biased near ground potential (AVSS) and should not receive any external dc biasing.
IF FILTER AND AGC
The PT9120 also requires 2 external IF filters at the mixer output for channel selection and to reject image frequency
noise at the input of the sub-sampling 2-bit A/D converter. These filters should have a bandwidth of at least 2MHz,
centered at the 1st IF corresponding to the frequency plan chosen (see Supported frequency plans), and should also
provide a low impedance path to ground at the local oscillator frequency.
A typical GPS receiver application may include the 4th order L-C band-pass filter connected between the IF1P/IF1N and
IF2P/IF2N pins as shown in the application circuit of Typical PT9120 RF application circuit schematic. With the
component values shown, the filter is centered at 20.46MHz and has a bandwidth of roughly 4MHz to accommodate
component tolerances of ±5%. On the PCB, the IF filter components should be placed far away from digital signals.
The IF- amplifier provides roughly 70dB of gain and includes 60dB of AGC range, which is sufficient to accommodate a
wide range of input signals without saturation. The AGC is calculated from MAG bit and sets the gain of the 1st IF
amplifier to achieve a logic HIGH duty cycle of 33% on the MAG bit output. The time constant of the AGC loop is
calculated from MAG bit set using a capacitor connected to the AGC pin.
DIGITAL INTERFACE
The reference clock input/output pin (CP) and the 2-bit AD converter’s digital output pins (SGN and MAG) are
CMOS-level compatible with a low-to-high logic swing from DVSS to DVDD. The SGN and MAG outputs represent the
sign and the magnitude bits, respectively, of the digitized (2-bit) 2nd IF signal. The 4 possible levels for both SGN and
MAG are coded as shown in Coded SGN and MAG output signal.
SGN
MAG
Value
LOW
HIGH
+3
LOW
LOW
+1
HIGH
LOW
-1
HIGH
HIGH
-3
The SGN and MAG output bits change on the falling edge of CP and should be read in by the baseband processor on the
rising edge of CP as illustrated in SGN and MAG output timing diagram.
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