PT9120_10 Datasheet, PDF (5/12 Pages) Princeton Technology Corp – GPS Receiver RF Front End IC

PT9120
FUNCTION DESCRIPTION
The PT9120 low power GPS receiver IC employs a double-conversion, super-heterodyne receiver topology to achieve
excellent performance. A complete GPS L1-band receiver front-end may be constructed using the PT9120 IC together
with an active antenna, RF and IF filters, and a reference crystal.
The PT9120 consists of an RF LNA; an RF mixer; complete frequency synthesizer including a VCO, phase/frequency
detector (PFD), charge pump, input and reference dividers, and a reference crystal oscillator; IF AGC amplifier; and a
2-bit A/D converter with CMOS-level outputs. The PT9120 includes an on-chip voltage regulator and an integrated
antenna detector and switch capable of supplying power to an active antenna as well as providing current limiting
protection when an antenna open or short has been detected. The on-chip voltage regulator provides a stable 1.9V
output at the VB pin. In addition, the PT9120 implements four distinct operating modes including two low power modes
and one complete power-down mode.
The application circuit includes the PT9120 IC and provides an option for either a patch antenna or active antenna, a
single connector to a power supply, power-down control inputs, and digital data outputs. Among the various external
parts are an external LNA, filter and oscillator components (TCXO), de-coupling resistors and capacitors for the analog
and digital power supplies, and the SAW filter between the discrete LNA output and the PT9120 RF input.
ANTENNA DETECTOR/SWITCH
The PT9120 integrates an antenna detector and switch to supply power to and control an optional active antenna. The
supply voltage for an active antenna is applied to the PT9120’s PVDD pin. The actual voltage supply connection to the
antenna is available on the AON pin. An external resistor between PVDD and ISNS is used to set the “antenna short”
and “antenna open” current thresholds. The actual antenna current is derived from the measured voltage drop across
the external sense resistor. The minimum and maximum voltage drop thresholds are internally set to 36mV and 300mV,
respectively. For a 56Ω external sense resistor, these voltage drops correspond to minimum (“antenna open”) and
maximum (“antenna short”) current thresholds
I_min = 36mV/56Ω = 640µA and I_max = 300mV/56Ω = 5.35mA.
Once the PT9120 is set to the fully active mode, internal antenna detector circuitry determines whether an active
antenna is properly connected by monitoring the current consumed by the antenna. As long as the monitored current
falls within the range delineated by I_min and I_max, the AOK pin is set to logic HIGH, and an internal switch within the
PT9120 is closed to allow voltage to be supplied to the antenna from the AON pin. Otherwise, the AOK pin is set to logic
LOW, and additionally, if the voltage drop across the sense resistor is > 300mV, the output current thru the AON pin is
limited to a value around 10% above I_max.
If desired, the antenna switch may be bypassed by connecting the active antenna directly to the ISNS pin. Furthermore,
the antenna detector may be bypassed by shorting PVDD to ISNS (AOK will always be set to logic LOW). In both these
cases, the short circuit current-limiting protection circuit is disabled.
If no active antenna is used, PVDD must be connected to ground, while AON and ISNS may be connected to ground or
left open. In this case, the AOK pin will always be set to logic HIGH when the PT9120 is in fully active mode, and will be
set to logic LOW in all other modes.
EXTERNAL LNA
As shown in the application circuit, an off-chip cascade LNA (15dB gain and 1.5dB NF) may be used to amplify the
1575.42MHz L1 GPS RF input signal prior to sending it to the RF input of the PT9120. The input and output impedances
for the LNA are nominally 50Ω at 1575.42MHz.
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