PT9250 Datasheet, PDF (5/7 Pages) Princeton Technology Corp – 48-channel Single Chip GPS Receiver

Ball Name
I/O Type
Description
GPIO7(EXT_INT1)
I/O
GPIO7 / External interrupt input
GPIO6(EXT_INT0)
I/O
GPIO6 / External interrupt input
GPIO5
I/O
GPIO5
GPIO4
I/O
GPIO4
GPIO3 (CSIO_RDY)
I/O
GPIO3 / CSIO ready
GPIO2 (CSIO_CLK)
I/O
GPIO2 / CSIO clock
GPIO1 (CSIO_DO)
I/O
GPIO1 / CSIO data output
GPIO0 (CSIO_DI)
I/O
GPIO0 / CSIO data input
ICE Interface
ICE_CLK
I
ICE clock
ICE_TMS
I
ICE mode select
ICE_RST_n
I
ICE reset, active low.
ICE_TDI
I
ICE data input
ICE_TDO
O
ICE data output
System Interface
SYS_RST_n
I
System reset, active low
MODE0, MODE1
I
Test mode selection, pull low
CFG0,CFG1,CFG3
I
Configuration, pull low.
RTC_XO
O
RTC crystal clock output
RTC_XI
I
RTC crystal clock input
PLLTKO
O
PLL test clock output
Regulator
REG_EN
I
Regulator enable
REG_1V2
O
Regulator 1.2V output
VDEC
I
Voltage detect
Baseband Power Pins
VDD_REG
P
3.3V power supply for regulator
VSS_REG
G
Ground for regulator
AVDD_PLL
P
Analog 1.2V power supply for PLL circuit
AVSS_PLL
G
Analog Ground for PLL
VDD_RTC
P
1.2V power supply for RTC
VSS_RTC
G
Ground for RTC
VDD_IO
P
3.3V power supply for IO
VSS_IO
G
Ground for IO
VDD_K
P
1.2V power for internal logic core
VSS_K
G
Ground for internal logic
VDD_F
P
3.3V power supply for flash
VSS_F
G
Ground for flash
NC
Open
IO Types
I
Input(3.3V CMOS level)
O
Output (3.3V CMOS level)
IO
Bi-direction IO(3.3V CMOS level)
P
Power
G
Ground
PT9250
V1.2
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