PT9250 Datasheet, PDF (4/7 Pages) Princeton Technology Corp – 48-channel Single Chip GPS Receiver

PT9250
BALL DESCRIPTION
Ball Name
RF Interface
SGN
MAG
I/O Type
O
O
AOK
O
CP
I/O
RFXEN
I
RFXI
I
RFXO
O
VB
O
RFPLL
O
AON
O
LNI
I
ISNS
I
PVDD
O
LNO
O
RFIN
I
VBG
O
IF1P
O
IF1N
O
RFMODE
I
AGCCAP
I/O
P1
I
P0
I
RF Power Pins
DVSS
G
DVDD
P
AVDD
P
RF_GND
G
Flash Interface
E_D0 ~ E_D15
I/O
E_A0 ~ E_A17
O
E_CS_n
O
E_WR_n
O
E_OE_n
O
E_BYTE
I
E_RP
I
E_RYBY
O
RF Chip Interface
AFE_CLK
I
AFE_SGN
I
AFE_MAG
I
CPU Peripheral
GPIO15(OPPS)
I/O
GPIO14
I/O
GPIO13
I/O
GPIO12
I/O
GPIO11 (UATX1)
I/O
GPIO10 (UARX1)
I/O
GPIO9 (UATX0)
I/O
GPIO8 (UARX0)
I/O
Description
Quantized 2nd IF “sign” bit
Quantized 2nd IF “magnitude” bit
Active antenna status output (AOK = HIGH = active antenna
OK; AOK=LOW=active antenna either open or shorted)
Reference clock input/output
Crystal oscillator enable pin
(XEN=HIGH=enabled; XEN=LOW=disabled)
Crystal oscillator input
Crystal oscillator output
Regulator (1.9V) output
Charge pump output
Antenna switch-controlled supply voltage to active antenna
LNA input
Antenna detector current sense input
Supply voltage (active antenna)
LNA output
Mixer input
Band gap reference (1.23V) output
Differential first-stage IF amplifier output/differential IF AGC
input
Reference frequency mode select input
AGC capacitor connection. Sets the AGC time constant.
Power-down control pins
Ground (digital circuitry)
Supply voltage (digital circuitry)
Supply voltage (analog circuitry)
Ground (analog circuitry)
External Data bus bit 0 ~ 15
External Address bus bit 0 ~ 17
External memory chip select, active low
External memory write signal, active low
External memory output enable, active low
Byte mode
Reset of external memory
Ready / Busy output
RF chip clock input
RF chip sign data bit
RF chip magnitude data bit
GPIO15 / One pulse per-second
GPIO14
GPIO13
GPIO12
GPIO11 / UART 1 transmission data
GPIO10 / UART 1 receive data
GPIO9 / UART 0 transmission data
GPIO8 / UART 0 receive data
V1.2
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