PT6530 Datasheet, PDF (33/42 Pages) Princeton Technology Corp – LCD Driver IC

PT6530
6.15.2 PT6530 INTERNAL BLOCK STATES DURING THE RESET PERIOD
• Clock Generator
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined after
the S0 and S1 control data bits are transferred.
• Common Diver, Segment Driver & Latch
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• Key Scan
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled.
• Key Buffer
Reset is applied and all the key data is set to low.
• Serial Interface, Control Register, Shift Register
Block that are reset
V1.3
33
June 2010