PT6530 Datasheet, PDF (31/42 Pages) Princeton Technology Corp – LCD Driver IC

PT6530
6.13 VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET)
This circuit generates an output signal and resets the system when logic block power is first applied and when the
voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage
VDET, which is 2.3V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block
power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied
and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1ms. (see Figure 1 and
Figure 2.)
6.14 POWER SUPPLY SEQUENCE
The following sequences must be observed when power is turned on and off. (see Figure 1 and Figure 2.)
• Power on: Logic block power supply(VDD) on → LCD driver block power supply(VLCD) on.
• Power off: LCD driver block power supply(VLCD) off → Logic block power supply(VDD) off.
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off
at the same time.
6.15 SYSTEM RESET
The PT6530 supports the reset methods described below. When a system reset is applied, display is turned off, key
scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning
become possible.
6.15.1 RESET METHODS
(1) Reset at power-on and power-down
If at least 1ms is assured as the logic block supply voltage VDD rise time when logic block power is applied, a system
reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1ms is
assured as the logic block supply voltage VDD fall time when logic block power drops, a system reset will be applied in
the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the
point when all the serial data (1/3 duty: the display data D1 to D228 and the control data, 1/4 duty: the display data D1 to
D300 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data,
after all the direction data has been transferred. However, the above operations will be performed regardless of the state
(high or low) of the /RES pin. If /RES is high, the reset will be cleared at the point the above operations are completed.
On the other hand, if /RES is low, the system will remain in the reset period as long as /RES is not set high, even if the
above operations are completed. (see Figure 1 and Figure 2.)
(2) Reset when the logic block power supply voltage is in the allowable operating range (VDD=3.0 to 6.0V).
The system is reset when the /RES pin is set low, and the reset is cleared by setting /RES pin high.
V1.3
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June 2010