PT6520 Datasheet, PDF (27/27 Pages) Texas Instruments – 8-A 5-V/3.3-V Input Adjustable ISR with Short-Circuit protection

LCD Driver IC
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PT6520
Symbol
C
L
L1
A
A1
A2
b
R1
R2
θ
θ
θ2
θ3
S
D
D1
D2
E
E1
E2
e
Min.
0.11
0.73
-
-
0.25
2.50
0.22
0.13
0.13
0º
0º
5º
5º
0.20
Nom.
-
0.88
1.60
-
-
2.70
-
-
-
-
-
-
-
-
23.20 BSC.
20.00 BSC.
18.85 REF.
17.20 BSC.
14.00 BSC
12.35 REF.
0.65 BSC.
Max.
0.23
1.03
-
3.40
0.50
2.90
0.40
-
0.30
7º
-
16º
16º
-
Notes:
1. All dimensioning and tolerancing conform to ASME Y14.5M-1994
2. Dimensions “D1” and “E1” do not include mold protrusion, allowable protrusion is 0.25 mm per side,
dimensions “D1” and “E1” do include mold mismatch and are determined at datum plane “H”.
3. Dimensions “D1” and “E1” do not include mold protrusion, allowable protrusion is 0.25 mm per side,
dimensions “D1” and “E1” do include mold mismatch and are determined at datum plane “H”.
4. Details of Pin 1 identifier are optional but must be located within the zone indicated.
5. Regardless of the relative size of the upper and lower body sections, dimensions “D1” and “E1” are
determined at the largest feature of the body exclusive of mold flash and gate burrs but including any
mismatch between the upper and lower sections of the molded body.
6. All dimensions are in millimeters.
7. Dimension “b” do not include dambar protrusion. The dambar protrusion(s) shall not cause the lead
width to exceed “B” maximum by more than 0.08 mm. Dambar cannot be located on the lower
radius or the lead foot.
8. “A1” is defined as the distance from the seating plane to the lowest point of the package body.
9. Refer to JEDEC MS-022 Variation GC-1.
JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT6520 V1.6
- 27 -
February, 2006