PT6520 Datasheet, PDF (22/27 Pages) Texas Instruments – 8-A 5-V/3.3-V Input Adjustable ISR with Short-Circuit protection

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LCD Driver IC
PT6520
READ/WRITE TIMING FOR THE 68-PORT MPU
(Ta=25℃, VDD=0V, VSS=-5V)
Parameter
Signal Symbol Condition
System cycle time
tCYC6
VSS=-5V
VSS=-3V
Address set-up time
A0, CS
R/W
tAW6
VSS=-5V
VSS=-3V
Address hold time
tAH6
VSS=-5V
VSS=-3V
Control pulse width
tDS6
VSS=-5V
VSS=-3V
Data set-up time
tDH6
VSS=-5V
VSS=-3V
CL=100pF
Data hold time
D0~D7
tOH6
VSS=-5V
CL=100pF
VSS=-3V
CL=100pF
RD access time
tACC6
VSS=-5V
CL=100pF
VSS=-3V
Enable disable time
READ
WRITE
VSS=-5V
E
tew
VSS=-3V
VSS=-5V
VSS=-3V
Min. Typ. Max Unit
1000 - - ns
2000 - - ns
20 - - ns
40 - - ns
10 - - ns
30 - - ns
80 - - ns
160 - - ns
10 - - ns
20 - - ns
10 - 60 ns
20 - 120 ns
-
- 90 ns
-
- 180 ns
100 - - ns
200 - - ns
80 - - ns
160 - - ns
Note:
1. tCYC6 indicates the cycle during which CS/E are high; it does not indicate are cycle of the E signal.
CONTROL TIMING FOR 80-PORT/68-PORT MPU
(Ta=25℃, VDD=0V, VSS=-5V)
Parameter
Signal
Symbol
Condition
Reset time
RES
tR
VSS=-5V
VSS=-3V
Reset time
(68-Port)
RES
tR1
VSS=-5V
VSS=-3V
Reset time
(80-Port)
RES
tR2
VSS=-5V
VSS=-3V
Min. Typ. Max Unit
1 - 750 µs
1.5 - 1000 µs
1
-
-
µs
1.5 - - µs
1
-
-
µs
1.5 - - µs
Note:
1. The input timing of the FR delay time is determined by the PT6520 (Slave)
2. The output timing of the FR delay time is determined by the PT6520 (Master)
PT6520 V1.6
- 22 -
February, 2006