PT6554_10 Datasheet, PDF (18/30 Pages) Princeton Technology Corp – LCD Driver IC

PT6554
VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET)
The Voltage Detection Type Reset Circuit generates an output signal and resets the system when power is applied for
the first time and when voltage drops (that is, for example, the power supply voltage is less than or equal to the power
down detection voltage (VDET=3.0V typ).) To ensure that this reset function works properly, it is recommended that a
capacitor be connected to the power supply line such that both the power supply voltage (VDD) rise time when power is
first applied and the power supply voltage (VDD) fall time when the voltage drops are at least 1ms.
SYSTEM RESET
If the supply voltage (VDD) rise time when power is first applied is at least 1ms, then the VDET output signal will initiate
a system reset when the supply voltage is increased. Likewise, if the supply voltage (VDD) fall time when power drops is
at least 1ms, then the VDET output signal will initiate a system reset when the supply voltage is decreased. It must be
noted that the reset function is cleared at the point when all the serial data (Display Data – D1 to D164 and the control
data) have been completely transferred. Please refer to the figure below.
Power supply voltage VDD rise time: t1 > 1ms
Power supply voltage VDD fall time: t2 > 1ms
During the reset period, the internal states of the various blocks of PT6554 are enumerated below. It should be noted
that the Address Interface, Control Register and the Shift Register Blocks are not reset during this period since serial
data transfer is possible. (Please also refer to the Block Diagram Section)
CLOCK GENERATOR BLOCK
When the reset function is applied, the base clock is terminated. The state of the OSC pin (either Normal or Sleep Mode)
is determined after the control bits – S0 and S1 have been transferred.
COMMON DRIVER, SEGMENT DRIVER & LATCH BLOCKS
When the reset function is applied the display is turned OFF. It should be noted, however, that the display data may be
inputted to the latch circuit during the reset period.
KEY SCAN BLOCK
When the reset function is applied, the key scan circuit is set to the initial state and the key scan operation is disabled.
KEY BUFFER BLOCK
When the reset function is applied, all the key data are set to “LOW”.
CONTROL REGISTER & SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
V1.4
18
June 2010