PE99155 Datasheet, PDF (8/15 Pages) Peregrine Semiconductor – Radiation Hardened UltraCMOS Monolithic Point-of-Load Synchronous Buck Regulator with Integrated Switches

Accurate Voltage Reference
The PE99155 contains an accurate 1.000V reference
which is used to drive an accurate output voltage. The
1.000V reference is trimmed at the factory to within ±1%
of 1.000V at 25°C.
Soft start
The soft start circuit uses the voltage on the SSCAP pin
to limit (pull down) the external VREF pin. This allows
the designer to limit the output voltage ramp rate.
Voltage tracking is specified on the VREF pin for
applications that require an external tracking capability.
The SSCAP pin is internally connected to a 16 pF (typ)
cap to ground and to a 3V internal rail through a 1.2 MΩ
(typ) resistor. When the SDb pin is low, the SSCAP pin
is pulled to ground by a 12 KΩ (typ) resistor. When the
shutdown signal is released the pull down switch is
released and the voltage on the SSCAP pin begins to
ramp up toward 3V. The ramp rate can be increased by
tying the SSCAP pin to the 5V input rail through an
external resistor. The pin is 5V capable. The ramp rate
can also be slowed by connecting the SSCAP pin to
ground through a supplemental capacitor.
Under Voltage Lockout
An internal under voltage lockout feature prevents the
PE99155 from powering up before input voltage rises
above the UVLO threshold of 4.2V (typ). 400 mV (typ) of
hysteresis is built-in to prevent false-triggering of the
UVLO circuit. The under voltage lockout must be cleared
and the SDb pin must be released before the part will be
enabled.
Power Good Flag
The PGOOD pin is an open drain output that can be
used to sense when the output voltage of the converter
has converged to within 10% (typ) of it’s final value. This
pin can also be used to provide limited power
sequencing when cascaded with the SDb pin of another
PE99155 part.
Internal circuitry senses when the voltage at the EAINM
pin has reached to within 10% (typ) of an internal 1.000V
reference voltage. When this happens, an internal
counter begins counting reference clock cycles and
continues counting as long as this condition remains
true. When the counter has reached 64, the circuit will
assert PGOOD.
PE99155
Product Specification
When EAINM exits the PGOOD window, there is a
30 mV (typ) hysteresis to prevent chatter when entering
or exiting the window. If during the count, the EAINM pin
exits the PGOOD threshold, the counter is reset,
PGOOD is not asserted and the count will begin again
when EAINM re-enters the PGOOD window.
When exiting the PGOOD state, once EAINM is outside
of the PGOOD threshold window, an internal counter
begins counting and will de-assert PGOOD when it
counts 64 reference clock cycles. If during the count, the
EAINM pin re-enters the PGOOD threshold, the counter
is reset, PGOOD is not de-asserted and the count will
begin again when EAINM exits the PGOOD window.
Synchronous (External Reference) or
Asynchronous (Internal Reference) Switching
Frequency
The PE99155 contains an internal oscillator capable of
operating at 1 MHz when the SYNC pin is tied to V_IN or
left open or at 500 kHz when the SYNC pin is tied to
ground. This reference clock is used in the current mode
control loop to time the rising edge of the OUT pin and
as a global internal clock reference. When the SYNC pin
is actively clocked at a rate of 100 kHz to 5 MHz, the
internal oscillator uses the clocked sync pulse train as
the global internal clock reference.
Whether operating synchronously or asynchronously,
the open drain SYNCOb pin contains the inverted
internal clock reference. This inverted clock signal can
be used to aid in the design of polyphase (n=2) power
supplies.
©2011-2012 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0307-07 │ UltraCMOS^® Power Management Solutions