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PE9601 Datasheet, PDF (4/14 Pages) Peregrine Semiconductor Corp. – 2200 MHz UltraCMOS™ Integer-N PLL for Rad Hard Applications
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PE9601
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name Interface Mode
30
fp
ALL
31
VDD-fp
ALL
32
Dout
Serial, Parallel
33
VDD
ALL
Type
Output
(Note 2)
Output
(Note 1)
34
Cext
ALL
Output
35
VDD
ALL
36
CP
ALL
37
NC
ALL
(Note 1)
Output
(Note 4)
Description
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
VDD for fp.
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Same as pin 1.
Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kW series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Same as pin 1.
Charge pump current is sourced for “up” when fc leads fp and sinked for “down”
when fc lags fp.
No connection.
38
VDD-fc
ALL
39
fc
ALL
40
GND
ALL
(Note 2)
Output
VDD for fc.
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
Ground.
41
GND
ALL
Ground.
42
fr
ALL
Input
Reference frequency input. See Figure 4.
43
LD
ALL
Output,
OD
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD
is high impedance, otherwise LD is a logic low (“0”).
44
Enh
Serial, Parallel
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Note 1: VDD pins 1, 11, 12, 23, 33, and 35 are connected by diodes and must be supplied with the same positive voltage level.
Note 2: VDD pins 31 and 38 are used to enable test modes and should be left floating.
Note 3: All digital input pins have 70k Ω pull-down resistors to ground.
Note 4: No connect pins can be left open or floating.
Figure 4. Looking into the device PIN 42 - fr
PIN 42
125K
2.8pF
©2010 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 14
Document No. 70-0025-06 │ UltraCMOS™ RFIC Solutions
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