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PE9601 Datasheet, PDF (10/14 Pages) Peregrine Semiconductor Corp. – 2200 MHz UltraCMOS™ Integer-N PLL for Rad Hard Applications
PE9601
Product Specification
The double buffering provided by the primary and
secondary registers allows for “ping-pong” counter
control using the FSELS input. When FSELS is
“high”, the primary register contents set the
counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B0 to
B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
7. After the falling edge of E_WR, the data
provide control bits as shown in Table 8 with bit
functionality enabled by asserting the Enh input
“low”.
Table 7. Primary Register Programming
Interface
Mode Enh
Parallel 1
Bmode Smode R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1
0
0 M2_WR rising edge load
M1_WR rising edge load
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
M0 R3 R2 R1 R0 A3 A2 A1 A0
A_WR rising edge load
D0 D7 D6 D5 D4 D3 D2 D1 D0
Serial*
1
0
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10 B11 B12 B13 B14 B15 B16 B17 B18 B19
Direct
1
1
X
0
0
0
0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode Enh
Parallel 0
Serial*
0
Bmode Smode
X
0
X
1
Reserved
D7
B0
Reserved
D6
B1
Reserved
D5
B2
Power
down
Counter
load
E_WR rising edge load
D4
D3
B3
B4
MSEL
output
D2
B5
Prescaler
output
D1
B6
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
fc, fp OE
D0
B7
MSB (first in)
(last in) LSB
©2010 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 14
Document No. 70-0025-06 │ UltraCMOS™ RFIC Solutions