PE9704 Datasheet, PDF (3/10 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

PE9704
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name Interface Mode Type
Description
17
GND
Both
CLOCK
Serial
18
M6
Direct
Input
Input
Ground
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of
CLOCK.
M Counter bit6
19
M7
Direct
Input
M Counter bit7
20
M8
Direct
Input
M Counter bit8 (MSB)
21
A0
Direct
Input
A Counter bit0
22
DMODE
Both
Input
Selects direct interface mode (DMODE=1) or serial interface mode (DMODE=0)
23
VDD
Both
E_WR
Serial
24
A1
Direct
(Note 1)
Input
Input
Same as pin 1
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
A Counter bit1.
25
A2
Direct
Input
A Counter bit2
26
A3
Direct
Input
A Counter bit3 (MSB)
27
FIN
Both
Input
RF prescaler input from the VCO. 3.0 GHz maximum frequency.
28
GND
Both
Ground.
29
GND
Both
Ground.
30
N/C
No connect.
31
VDD
32
DOUT
33
VDD
Both
Serial
Both
(Note 1)
Output
(Note 1)
Same as pin 1
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to DOUT through enhancement register programming.
Same as pin 1
34
N/C
No connect.
35
GND
Both
36
PD_D
Both
37
PD_U
Both
Output
Ground.
PD_D pulses down when fp leads fc.
PD_U pulses down when fc leads fp.
38
VDD
39
CEXT
40
GND
Both
Both
Both
(Note 1)
Output
Same as pin 1
Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series
resistor. Connecting CEXT to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Ground
41
GND
Both
Ground
42
FR
43
ENH
44
LD
Both
Both
Serial
Input
Output, OD
Output
Reference frequency input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Lock detect output, the open-drain logical inversion of CEXT. When the loop is
locked, LD is high impedance; otherwise LD is a logic low (“0”).
Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.
Document No. 70-0083-03 │ www.psemi.com
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 10