PE9704 Datasheet, PDF (2/10 Pages) Peregrine Semiconductor Corp. – 3.0 GHz Integer-N PLL for Rad Hard Apllications

PE9704
Product Specification
Figure 2. Pin Configurations (Top View)
R₄
R₅
M₀
M₁
V_DD
V_DD
M₂
M₃
S_WR, M₄
DATA, M₅
GND
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
C_EXT
V_DD
PD_U
PD_D
GND
N/C
V_DD
D_OUT
V_DD
N/C
GND
Figure 3. Package Type
44-lead CQFJ
Table 1. Pin Descriptions
Pin No. Pin Name Interface Mode
Type
1
VDD
Both
2
R0
Direct
3
R1
Direct
4
R2
Direct
5
R3
Direct
6
GND
Both
7
R4
8
R5
9
M0
10
M1
11
VDD
12
VDD
13
M2
14
M3
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
S_WR
Serial
15
M4
Direct
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Input
Input
Input
DATA
Serial
16
M5
Direct
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0
R Counter bit1
R Counter bit2
R Counter bit3
Ground
R Counter bit4
R Counter bit5 (MSB)
M Counter bit0
M Counter bit1
Same as pin 1
Same as pin 1
M Counter bit2
M Counter bit3
Frequency register load enable input. Buffered data is transferred to the frequency
register on S_WR rising edge.
M Counter bit4
Binary serial data input. Data is entered LSB first, and is clocked serially into the
20-bit frequency control register (E_WR “low”) or the 8-bit enhancement register
(E_WR “high”) on the rising edge of CLOCK.
M Counter bit5
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 10
Document No. 70-0083-03 │ UltraCMOS™ RFIC Solutions