EPR-31 Datasheet, PDF (8/36 Pages) Power Integrations, Inc. – Engineering Prototype Report for EP-31 Multiple Output 180 W AC-DC Power

EPR-31 – Multi Output, 180 W, PC Main Power Supply
01-Feb-05
4 Circuit Description
With line feed-forward, duty factor reduction, a programmable primary current
limit, line sense for input under-voltage (UV) lockout and overvoltage (OV)
shutdown and a soft-start function for reduced stesses during start-up, all
integrated onto one monolithic IC, the TOPSwitch-GX family has all of the
functions necessary to operate as an off-line, single-ended forward converter.
Also, the TOPSwitch-GX family has sufficient power capability to address the PC
main application arena.
In this design, the Line sense (L) pin (see the TOPSwitch-GX data sheet for a
description of the L pin functions and uses) senses the rectified AC input voltage
through R3, R5, and R6, and inhibits the start of U1 switching until the minimum
input voltage [80 VAC (110 VAC Nom. line), 160 VAC (230 VAC Nom. line)] is
reached. When U1 begins switching, bias winding (T1, pin 3) current, delivered
through R13, D18, D19, R36 and R8, immediately sets a maximum duty factor
limit by injecting current into the L pin (see the TOPSwitch-GX data sheet for a
description of maximum duty cycle DC_MAX reduction operation). The L pin sums
current from two sources: directly from the line (R3, R5 & R6) and from the bias
winding (T1 pins 3–4, R13, D18, D19, R36, C22 and R8). The rectified forward
pulse from the bias winding develops a DC voltage across C22, which
determines the current that flows through R8 into the L pin. The L pin current
increases with line voltage and reduces the DC_MAX, preventing the possibility of
transformer saturation during line or load transients.
A TOP249Y device was selected for this application. Its primary current limit has
been programmed to about 3.5 A (via the X pin), by pull-down resistor R12,
which is connected (through Q7) to primary return (the SOURCE pin of U1) when
the supply is on (the U3 phototransistor is on and Q7 is saturated.). This limits
the peak output power that the load(s) can demand from this design to about
200 W.
When the AC input voltage drops below 75 V, a second UV lockout circuit (R4,
R14, R39 and Q1) activates preventing shutdown glitches. Transistor Q1 is
biased on when V_IN drops below 75 VAC. Its collector then pulls up the U1 X pin
(through R39), disabling its MOSFET from switching (see the TOPSwitch-GX
data sheet, Figure 11, for how the X pin can be used to enable/disable output
MOSFET switching).
The Zener clamp portion (D3, D4, and D5) of the primary snubber circuit only
conducts lightly during normal steady-state operation. Capacitor C4 is coupled to
the node of T1 and the DRAIN of U1 through a slow recovery diode (D1). This
very efficient snubber allows the highest possible flyback voltage to develop
during the U1-MOSFET off time, and recycles a significant amount of that energy
back through T1 (to C9 and the output) during the reverse recovery time of D1.
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