PO100HSTL11A Datasheet, PDF (1/6 Pages) Potato Semiconductor Corporation – 1 to 2 Differential Clock/Data Fanout Buffer

PO100HSTL11A
1 to 2 Differential Clock/Data Fanout Buffer
02/11/07
2.4V -3.6V Differential inputs to HSTL outputs Clock Buffer
FEATURES:
DESCRIPTION:
• Patented Technology
• Two HSTL differential outputs
• One pair of LVDS/LVPECL/HSTL/ differential
or single-ended inputs
• Operating frequency up to 1.24GHz with 2pf load
• Operating frequency up to 900MHz with 5pf load
• Operating frequency up to 400MHz with 15pf load
• Very low output pin to pin skew < 40ps
• Propagation delay < 2.0ns max with 15pf load
• 2.4V to 3.6V power supply
• Industrial temperature range: –40°C to 85°C
• Available in 8-pin SOIC package
• Available in 8-pin TSSOP package
Potato Semiconductor’s PO100HSTL11A is
designed for world top performance using
submicron CMOS technology to achieve 1.24GHz
HSTL output frequency with less than 2.0ns
propagation delay.
The PO100HSTL11A is a low-skew, 1-to-2
differential fanout buffer targeted to meet the
requirements of high-performance clock and data
distribution applications. The device has a fully
differential internal architecture that is optimized
to achieve low signal skews at operating frequen-
cies of up to 1.24GHz .
Pin Configuration
Q0
1
Q0
2
Q1
3
Q1
4
8
Vcc
7
D
6
D
5
GND
Logic Block Diagram
Q0
Q0
D
D
Q1
Q1
Pin Description
PIN
D, D
Q0, Q0, Q1, Q1
V_CC
GND
FUNCTION
LVDS LVPECL HSTL Inputs
HSTL Outputs
Positive Supply
Ground Supply
1
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