PM5361TUPP Datasheet, PDF (96/108 Pages) PMC-Sierra, Inc – SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR

PM5361 TUPP
DATA SHEET
PMC-920526
ISSUE 8
TRIBUTARY UNIT PAYLOAD PROCESSOR
Notes on Microprocessor Interface Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt
point of the reference signal to the 1.4 Volt point of the output.
2. Maximum output propagation delays are measured with a 100 pF load on the
Microprocessor Interface data bus, (D[7:0]).
3. a. In Intel mode, a valid read enable bar is defined as a logical OR of the CSB
and the RDB signals.
b. In Motorola mode, a valid read enable is defined as a logical AND of the E
signal, the RWB signal, and the inverted CSB signal.
4. Microprocessor Interface timing applies to normal mode register accesses
only.
5. In non-multiplexed address/data bus architectures, ALE should be held high,
parameters tS_ALR, tH_ALR, tV_L, and tS_LR are not applicable.
6. Parameters tH_AR and tS_AR are not applicable if address latching is used.
7. When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
8. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
Table 6
- Microprocessor Interface Write Access (Figure 19, Figure 20)
Symbol
tS_AW
tS_DW
tS_ALW
tH_ALW
tV_L
Parameter
Address to Valid Write Set-up Time
Data to Valid Write Set-up Time
Address to Latch Set-up Time
Address to Latch Hold Time
Valid Latch Pulse Width
Min Max Units
25
ns
20
ns
20
ns
20
ns
20
ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 88