PM5361TUPP Datasheet, PDF (19/108 Pages) PMC-Sierra, Inc – SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR

PM5361 TUPP
DATA SHEET
PMC-920526
ISSUE 8
TRIBUTARY UNIT PAYLOAD PROCESSOR
8 PIN DESCRIPTION
Pin Name Type
SCLK
Input
VCLK
IC1J1
Input
Pin Function
No.
153 The system clock (SCLK) provides timing for
TUPP internal operation. SCLK is a 19.44 MHz,
nominally 50% duty cycle clock.
The test vector clock (VCLK) signal is used
during TUPP production testing to verify internal
functionality.
44 The input C1/J1 frame pulse (IC1J1) identifies
the transport envelope and synchronous payload
envelope frame boundaries on the DIN[7:0] bus.
IC1J1 is set high while ISPE is low to mark the
first C1 byte of the transport envelope frame on
the DIN[7:0] bus. IC1J1 is set high while ISPE is
high to mark each of the J1 bytes of the
synchronous payload envelope(s) on the
DIN[7:0] bus. IC1J1 must be present at every
occurrence of the first C1 and all J1 bytes. The
TUPP will ignore a pulse on IC1J1 at the byte
position of the V1 byte of the first tributary of
each TUG3 or VC3. IC1J1 is sampled on the
rising edge of SCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 11