PM7367 Datasheet, PDF (86/323 Pages) PMC-Sierra, Inc – 32 link, 32 Channel Data Link Manager with PCI Interface

DATA SHEET
PMC-1991499
ISSUE 2
PM7367 FREEDM-32P32
FRAME ENGINE AND DATA LINK MANAGER
the request from the link with the highest priority for service. When there are no
pending requests, the priority encoder generates an idle cycle. In addition, once
every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no
requests are serviced. This cycle is used by the channel assigner downstream
for CBI accesses to the channel provision RAM.
8.8.3 Channel Assigner
The channel assigner block determines the channel number of the request
currently being processed. The block contains a 1024 word channel provision
RAM. The address of the RAM is constructed from concatenating the link
number and the time-slot number of the highest priority requester. The fields of
each RAM word include the channel number and a time-slot enable flag. The
time-slot enable flag labels the current time-slot as belonging to the channel
indicted by the channel number field. For time-slots that are enabled, the
channel assigner issues a request to the THDL block which responds with packet
data within one byte period of the transmit stream.
8.9 Performance Monitor
The Performance Monitor block (PMON) contains four counters. The first two
accumulate receive partial packet buffer FIFO overrun events and transmit partial
packet buffer FIFO underflow events, respectively. The remaining two counters
are software programmable to accumulate a variety of events, such as receive
packet count, FCS error counts, etc. All counters saturate upon reaching
maximum value. The accumulation logic consists of a counter and holding
register pair. The counter is incremented when the associated event is detected.
Writing to the FREEDM-32P32 Master Clock / BERT Activity Monitor and
Accumulation Trigger register transfer the count to the corresponding holding
register and clear the counter. The contents of the holding register is accessible
via the PCI interface.
8.10 JTAG Test Access Port Interface
The JTAG Test Access Port block provides JTAG support for boundary scan.
The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The FREEDM-32P32 identification code is
173670CD hexadecimal.
8.11 PCI Host Interface
The FREEDM-32P32 supports two different normal mode register types as
defined below:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE 72