PM7326 Datasheet, PDF (58/238 Pages) PMC-Sierra, Inc – ATM/PACKET Traffic Manager and Switch

DATA SHEET
PMC-1981224
ISSUE 6
PM7326 S/UNI APEX
ATM/PACKET TRAFFIC MANAGER AND SWITCH
Pin Name
WR
BURSTB
BLAST
READYB
Type
Pin
No.
Input F3
Input E2
Input D1
Tri-state F4
Function
Write/Read. The write/read (WR) signal is
evaluated when the ADSB and CSB are sampled
active by S/UNI APEX. The BUSPOL input pin
controls the polarity of this input.
WR is sampled on the rising edge of BCLK.
Burst Bar. This signal is evaluated when the ADSB
and CSB are sample active by S/UNI APEX. When
low, this signal indicates that the current access is a
burst access (and the BLAST input can be used to
detect the end of the transaction).
BURSTB is sampled on the rising edge of BCLK.
Burst Last. This signal indicates the last data
access of the transfer. When the BURSTB input is
low, the BLAST input is driven active during the last
transfer of a transaction (even if the transaction is
one word in length). When the BURSTB input is
high, the BLAST input is ignored by S/UNI APEX.
The BUSPOL input pin controls the polarity of this
input.
BLAST is sampled on the rising edge of BCLK.
Ready Bar. This signal is asserted low by S/UNI
APEX when the data on the AD[31:0] bus has been
accepted (for writes), or when the data on the
AD[31:0] is valid (for reads). This signal may be
used by S/UNI APEX to delay a data transaction.
This output is Hi-Z’d one clock cycle after an S/UNI
APEX access, allowing multiple slave device to be
tied together in the system. This output should be
pulled up externally.
READYB is updated on the rising edge of BCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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