PM7326 Datasheet, PDF (211/238 Pages) PMC-Sierra, Inc – ATM/PACKET Traffic Manager and Switch

DATA SHEET
PMC-1981224
ISSUE 6
PM7326 S/UNI APEX
ATM/PACKET TRAFFIC MANAGER AND SWITCH
17 FUNCTIONAL TIMING
17.1 Microprocessor Interface
The following diagrams illustrate the various handshaking required for
microprocessor reads and writes.
Figure 33 shows a single read and write operation with bus polarity set to 1. On
the first cycle, BURSTB is sampled inactive; therefore, it is expected that the
cycle be a single data transfer, and the BLAST signal is of no significance. The
subsequent 2 cycles have BURSTB sampled active hence the transfer cycle Is
terminated when both BLAST and READYB are asserted. Note that between
each transfer, there is a turn around cycle provided by the external interface to
ensure that there is no bus contention on back to back transfers on the AD bus.
Figure 33 - Single Word Read and Write
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
BCLK
Read, 3 wait cycles
Write, 1 wait cycle
Read, 4 wait cycles
BUSPOL
CSB
ADSB
AD(31:0)
A
D
A
D
A
D
WR
BURSTB
BLAST
READYB
BTERMB
Figure 34 shows a burst read and write operation with bus polarity set to 0. The
first and third access illustrate transfers that are terminated by the S/UNI APEX
via the assertion of BTERMB. The second and fourth access illustrate transfers
that are terminated by the external interface via the assertion of BLAST. Note
that between each transfer, there is no turn around cycle. Care must be taken to
examine the AC timing to ensure that there is no bus contention on the AD bus
between a read followed by a write transfer.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
195