PM4328 Datasheet, PDF (50/250 Pages) PMC-Sierra, Inc – High Density T1/E1 Framer with Integrated M13 Multiplexer

STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
ECLK[1]/EFP[1]/ESIG[1] I/O
ECLK[2]/EFP[2]/ESIG[2]
ECLK[3]/EFP[3]/ESIG[3]
ECLK[4]/EFP[4]/ESIG[4]
ECLK[5]/EFP[5]/ESIG[5]
ECLK[6]/EFP[6]/ESIG[6]
ECLK[7]/EFP[7]/ESIG[7]
ECLK[8]/EFP[8]/ESIG[8]
ECLK[9]/EFP[9]/ESIG[9]
ECLK[10]/EFP[10]/ESIG[10]
ECLK[11]/EFP[11]/ESIG[11]
ECLK[12]/EFP[12]/ESIG[12]
ECLK[13]/EFP[13]/ESIG[13]
ECLK[14]/EFP[14]/ESIG[14]
ECLK[15]/EFP[15]/ESIG[15]
ECLK[16]/EFP[16]/ESIG[16]
ECLK[17]/EFP[17]/ESIG[17]
ECLK[18]/EFP[18]/ESIG[18]
ECLK[19]/EFP[19]/ESIG[19]
ECLK[20]/EFP[20]/ESIG[20]
ECLK[21]/EFP[21]/ESIG[21]
ECLK[22]/EFP[22]/ESIG[22]
ECLK[23]/EFP[23]/ESIG[23]
ECLK[24]/EFP[24]/ESIG[24]
ECLK[25]/EFP[25]/ESIG[25]
ECLK[26]/EFP[26]/ESIG[26]
ECLK[27]/EFP[27]/ESIG[27]
ECLK[28]/EFP[28]/ESIG[28]
AB3 Egress Clock (ECLK[1:28]). When the Clock
Y4 Master mode is active, ECLK[x] is an output
Y19 and is used to sample the associated egress
AA21 data, ED[x]. ECLK[x] is a version of the
AB22 transmit clock[x] which is generated from the
V22 receive clock or the common transmit clock,
T21 CTCLK.
T22
AB1
T1
G2
G3
U21
V19
D21
When in Clock Master: NxChannel mode,
ECLK[x] is gapped during the framing bit
position and optionally for between 1 and 23
DS0 channels or 1 and 32 channel timeslots in
the associated ED[x] stream. When Clock
Master: Clear Channel is active ECLK[x] is not
gapped.
C21 ^{When in Clock Slave: Clear Channel mode}
U4 ^{this input is an input and is used to sampled}
R1 ^ED[x].
D3 _{ED[x] is sampled on the active edge of the}
F1 _{associated ECLK[x].}
T20
U22 ^{Egress Frame Pulse (EFP[1:28]). When the}
B22 ^{Clock Slave: EFP Enabled mode is active, the}
D20 ^{EFP[1:28] outputs indicate the frame}
L3 ^{alignment or the superframe alignment of}
K4 ^{each of the 28 framers.}
E4 _{EFP[x] is updated on the active edge of}
F2 _CECLK.
Egress Signaling (ESIG[1:28]). When the
Clock Slave: External Signaling mode is
active, the ESIG[1:28] input carries the
signaling bits for each channel in the transmit
data frame, repeated for the entire superfram’.
Each channel’s signaling bits are in bit
locations 5,6,7,8 of the channel and are
frame-aligned by the common egress frame
pulse, CEFP.
ESIG[x] is sampled on the active edge of
CECLK.
PROPRIETARY AND CONFIDENTIAL
37