PM4328 Datasheet, PDF (110/250 Pages) PMC-Sierra, Inc – High Density T1/E1 Framer with Integrated M13 Multiplexer

STANDARD PRODUCT
DATASHEET
PMC-2011596
ISSUE 1
PM4328 TECT3
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
When the TECT3 is the SBI egress clock master for a link, clocks are sourced
within the TECT3. Based on buffer fill levels, the EXSBI sends link rate
adjustment commands to the link source indicating that it should send one
additional or one fewer bytes of data during the next 500uS interval. Failure of
the source to respond to these commands will ultimately result in overflows or
underflows which can be configured to generate per link interrupts.
Channelized T1s extracted from the SBI bus optionally have the channel
associated signaling (CAS) bits explicitly defined and carried in parallel with the
DS0s, but only if the SBI interface is configured for synchronous mode
operation.
Note that ITU-T G.747 mutiplexed E1 streams are not supported over the SBI
interface. The E1 mode of operation is restricted to using the serial clock and
data or H-MVIP system interfaces.
9.31 Insert Scaleable Bandwidth Interconnect (INSBI)
The Insert Scaleable Bandwidth Interconnect block maps up to 28 1.544Mb/s
links or a single 44.736Mb/s link into the SBI shared bus. The 1.544Mb/s links
can be unframed when sourced directly from the DS3 multiplexer, or they can be
T1 channelized when sourced by the T1 framers. The 44.736Mb/s link can also
be unframed when sourced directly from the DS3 interface. The 44.736Mb/s link
can be an unchannelized DS3 when sourced from the DS3 framer.
Links inserted into the SBI bus can be timed from the TECT3 or from the far end.
The INSBI makes link rate adjustments by adding or deleting an extra byte of
data over a 500uS interval based on buffer fill levels. Timing adjustments made
by the INSBI are detected by the receiving SBI interface by explicit signals in the
SBI bus structure.
The INSBI optionally sends link rate information across the SBI bus. This
information is used by the receiving SBI interface to create a recovered link clock
which is based on small clock phase adjustments signaled by the INSBI.
Channelized T1s inserted into the SBI bus optionally have the channel
associated signaling (CAS) bits explicitly defined and carried in parallel with the
DS0s or timeslots, but only if the SBI interface is configured for synchronous
mode operation. When enabled for CAS insertion the INSBI takes a byte serial
stream of CAS bits from the SBISIPO and inserts them into the SBI bus
structure.
Note that ITU-T G.747 mutiplexed E1 streams are not supported over the SBI
interface. The E1 mode of operation is restricted to using the serial clock and
data or H-MVIP system interfaces.
PROPRIETARY AND CONFIDENTIAL
97