PM7345S Datasheet, PDF (37/306 Pages) PMC-Sierra, Inc – SATURN USER-NETWORK INTERFACE FOR ATM PLESIOCHRONOUS DIGITAL HIERARCHY DATACOM

DATA SHEET
PMC-931011
RFIFOE/
RCA/
FRCLK
PM7345 S/UNI-PDH
ISSUE 6
SATURN USER-NETWORK INTERFACE
Output 52 54 Receive FIFO Empty (RFIFOE). RFIFOE indicates
the receive FIFO status. RFIFOE is logic 1 when
the cell-based FIFO is empty and logic 0 when the
FIFO contains at least 1 cell. RFIFOE timing is
applicable when using the asynchronous FIFO
interface in the S/UNI-PDH (either in the 84-pin
PLCC or when SYFIFOB is tied to logic 1 in the
100-pin package). Note that with the asynchronous
FIFO interface RFIFOE transitions from empty to full
(logic 1 to logic 0) on write cell boundaries with
timing derived from the RCLK input. RFIFOE
transitions from full to empty (logic 0 to logic 1) on
read cell boundaries on the rising edge of FRDB.
RFIFOE should be treated by the ATM layer as a
purely asynchronous signal.
Receive Cell Available (RCA). RCA is available in
the 100-pin PQFP package when SYFIFOB is tied
to logic 0. When the synchronous FIFO interface is
used, RCA is an active high signal and is logic 1
when the cell-based FIFO contains at least 1 cell
and is logic 0 when the cell-based FIFO is empty.
RCA can be enabled to transition low when the
FIFO is empty (default) or when the FIFO is 4 bytes
away from being empty (almost empty), as
controlled by the REMPTY4 register bit. RCA
transitions on rising edges of the RFCLK.
Receive Cell Clock (FRCLK). FRCLK is derived
from RCLK when the receive FIFO is bypassed (the
FIFOBP bit in the S/UNI-PDH Configuration
Register is logic 1). FRDATA[7:0], LOF, OOF, and
RSOC are updated on the falling edge of FRCLK.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 23