PM5313 Datasheet, PDF (235/646 Pages) PMC-Sierra, Inc – SONET/SDH Payload Extractor/Aligner for 622 Mbit/s Interfaces

PRODUCTION
DATASHEET
PMC-1981162
ISSUE 6
PMC-Sierra, Inc.
PM5313 SPECTRA-622
SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S
SENB:
The loss of signal transition detector enable (SENB) bit enables the
declaration of loss of transition (LOT) when more than 95 consecutive ones or
zeros occurs in the receive data. When SENB is a logic zero, a loss of
transition is declared when more than 95 consecutive ones or zeros occurs in
the receive data or when the SD input is low. When SENB is a logic one, a
loss of transition is declared only when the SD input is low.
PFPEN:
The parallel frame pulse enable (PFPEN) enables the parallel frame pulse
operation when the parallel data interface is enabled (LIFSEL set high or
PDLE set high). When PFPEN is a logic zero, the input frame pulse is ignored
and the SONET framing is performed on the PIN[7:0] data. When PFPEN is a
logic one, the SONET framer is ignored and the PIN[7:0] bus is assumed to
be byte aligned marked with the input frame pulse (FPIN). PFPEN is ignored
when the parallel data interface is disabled.
SDINV:
The signal detect input invert (SDINV) controls the polarity of the SD input.
The value of the SD input is logically XOR’ed with the value of the SDINV
register. Therefore, when SDINV is a logic zero, valid signal power is
indicated by the SD input high. When SDINV is a logic one, valid signal power
is indicated by the SD input low.
PROPRIETARY AND CONFIDENTIAL
203