PM5357 Datasheet, PDF (221/432 Pages) PMC-Sierra, Inc – 622 Mbit/s ATM and Packet Over SONET Physical Layer Device

PRODUCTION
S/UNI-622-POS
DATASHEET
PMC-1980911
ISSUE 5
PMC-Sierra, Inc.
PM5357
S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
Register 0x5A: CSPI Clock Synthesis Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
CSURESET
CSURESETLPF
Reserved
Unused
Reserved
Reserved
Reserved
Default
0
0
0
0
X
0
0
0
The CSU Control register provides direct access to the CSU. When the CSU
does not lock properly (ROOLV remains high), the CSU may be re-initialized
using this register.
When the AVD power supply of the S/UNI-622-POS is subjected to a change
greater than the ±5% tolerance specified for the 3.3V analog supply pins, the
Clock Synthesis Unit may lose lock to the reference clock. When this occurs, the
ROOLV will remain high until the CSU is reset using the CSURESETLPF and
CSURSET registers.
The S/UNI-622-POS will operate normally if the power supply does not vary
beyond the specified ±5% tolerance.
CSURESETLPF:
The CSU low pass filter (LPF) reset control CSURESETLPF bit provides a
software reset for the CSU-622 ABC. When CSURESETLPF is set high, the
CSU RESETLPF input is set high forcing the CSU LPF into reset. When
CSURESETLPF is set low, the CSU RESETLPF input is controlled by the
system reset.
The CSURESETLPF and CSURESET should be held high for 10ms to
properly reset the CSU.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE
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