PM7351 Datasheet, PDF (138/174 Pages) PMC-Sierra, Inc – Octal Serial Link Multiplexer

RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
1. There is considerable latency between the bus master seeing the TPA
asserted and when it initiates the cell transfer to the S/UNI-VORTEX. For
example the bus master (typically an ATM switching device) may have to
perform a lookup, fetch the cell out of external memory, place the cell into
an output buffer in the switching device, etc..
2. The system bus is running at the same rate (or only slightly faster) than
the LVDS link, and hence it takes a relatively long time to write the cell into
the buffer.
To assist the designer in these “tight timing” scenarios the S/UNI-VORTEX allows
the value of FREADY[5:0] to be adjusted. To understand how this helps, let us
step through the sequence of events that determine when a particular
downstream buffer’s TPA (Transmit Packet Available) status is asserted and
deasserted:
1. If the channel’s buffer is empty when the channel is polled, then TPA is
asserted. At some point after seeing TPA asserted the bus master will
start its write into the channel’s downstream buffer.
2. TPA status is deasserted when the first write into the buffer occurs. With
the default extended length Any-PHY cells (PHY address in Word 0), the
cell can be directed into the buffer immediately after Word 0 is available.
Hence TPA is deasserted starting with Word 1 of the cell transfer.
However, if the shorter cell length option is enabled and the H5/UDF field
contains the PHY address (i.e. INADDUDF = 1 in the Downstream Cell
Interface Configuration register) then TPA is deasserted after nine cycles
after the last word of the cell is written. This must be taken into account
by the bus master device when establishing the polling algorithm to be
used when INADDUDF=1.
3. At some point after the entire cell has been written into the buffer, the
downstream LVDS link scheduler will put this channel at the head of the
queue and start to serialize and send the buffer contents downstream on
the LVDS link. As mentioned previously, the entire cell must be present in
the buffer before it is eligible for scheduling onto the LVDS link. The cell
will be read out of the buffer at the LVDS line rate, not the line rate of the
far-end PHY. The far-end S/UNI-DUPLEX provides a shallow rate
decoupling buffer for each PHY, thereby allowing the LVDS link to run full
speed for even the slowest PHYs.
4. The TPA status for that buffer is reasserted once the number of bytes
defined in the link’s FIFO Ready Level (FREADY[5:0]) field have been
serialized and sent down the link. If the FREADY[5:0] is set to a value
greater than or equal to the cell length then FREADY has no real effect –
that channel’s TPA status will remain deasserted until the entire cell has
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 128